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Static Timing Design Engineer – Chip STA & Flows
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-08-09
Listing for:
Amazon
Full Time
position Listed on 2026-08-09
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
Amazon is seeking a skilled Timing Analysis Engineer to design and optimize timing analysis flows for blocks and full-chip RTL-to-GDSII. You will develop and validate constraints, run STA, and guide fixes with ECOs, while scripting automation to generate reports.
The role requires 1+ year in STA and timing constraint development, plus scripting in Tcl/Perl/Python, with a BS/MS/PhD in EE/CS and strong collaboration with RTL/Arch teams.
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