System--Chip; SoC) Physical Design Engineer

Location United States

Employment Type:

Full-time

Education:

B.S. in Electrical Engineering

Experience:

5+ years

We are seeking an experienced System-on-Chip (SoC) Physical Design Engineer to drive advanced-node designs from floor planning through place and route, timing closure, physical verification, power integrity, signoff, and tapeout. The ideal candidate is highly hands-on, technically strong, and able to independently diagnose complex implementation issues while collaborating closely with front-end, verification, DFT, package, CAD, and foundry teams.

Own the complete SoC physical design flow from netlist and UPF handoff through floor planning, placement, CTS, routing, ECO, timing closure, physical verification, signoff, and tapeout.

Perform chip/block floor planning, macro placement, I/O and pin planning, power-domain planning, power-grid design, congestion analysis, and routing-resource planning.

Drive place and route, physical optimization, CTS, routing, and ECO implementation using Cadence Innovus.

Drive timing closure across multiple modes and PVT corners using Prime Time or Tempus with MMMC methodologies.

Set up, run, debug, and close Calibre LVS, DRC, antenna, wirebond, and WLCSP checks; interpret foundry rules and implement manual or automated fixes in Innovus.

Perform RC extraction with Quantus and IR-drop/electromigration analysis with Voltus.

Perform RTL- and gate-level power analysis using Cadence Joules.

Collaborate with RTL and verification engineers using Xcelium or VCS waveforms to debug logic, timing, and integration issues.

Use AI responsibly to find innovative solutions that save cycle time and reduce human errors.

Participate in tapeout readiness reviews and ensure completion of timing, physical verification, power integrity, low-power, and foundry signoff requirements.

B.S. degree in Electrical Engineering.

Minimum 5 years of hands-on SoC or ASIC physical design experience, including floor planning, place and route, ECO, timing closure, physical verification, and tapeout.

Advanced-node tapeout experience, preferably including 22 nm, 12 nm, and 7 nm technologies.

Extensive hands-on experience with Cadence Innovus.

Hands-on experience with UPF low-power design flow from synthesis through place and route; able to develop and debug UPF based on architectural, RTL power-domain specifications, and power intent.

Able to set up and run logic synthesis using Synopsys Design Compiler or Cadence Genus.

Extensive static timing analysis and timing closure experience using Synopsys Prime Time or Cadence Tempus.

Extensive CTS experience in Innovus, including clock-tree tuning and balancing for skew, latency, power, and robustness across PVT corners.

Logic equivalence check (LEC) using Conformal.

Good familiarity with DFT concepts and related physical design methodologies such as scan chain reordering, power analysis/timing analysis modes, etc.

Hands-on experience setting up and running Siemens Calibre LVS, DRC, antenna, wirebond, and WLCSP checks.

Ability to read and interpret foundry design rule manuals and resolve DRC issues manually or through automated Innovus flows.

Experience using Cadence Quantus for RC extraction.

Experience using Cadence Voltus for static/dynamic IR-drop and electromigration analysis.

Experience using Cadence Joules for RTL- and gate-level power analysis.

Familiarity with RTL and gate-level simulation using Cadence Xcelium or Synopsys VCS and ability to analyze waveforms with front-end engineers.

Strong understanding of SDC, generated clocks, clock groups, false paths, multicycle paths, derates, OCV/AOCV/POCV, setup/

Experience with 22nm, 12nm, 7nm design rules, physical design flows, standard cells, memories, PVT corners and their characteristics, and pitfalls.

Low-power implementation: deep knowledge of, and implementation experience of, power domains, isolation, level shifters, retention, power switches, always-on logic, and power-state tables.

Logic equivalence checking: able to set up tool scripts and debug/resolve non-equivalence for RTL vs. RTL, RTL vs. gate, and gate vs. gate, with UPF.

Physical design optimization: congestion, utilization, routability, area, leakage, dynamic power, and manufacturability.

Signal integrity: crosstalk, coupling capacitance, noise, shielding, spacing, layer assignment, and delta-delay effects.

Power-grid design and optimization, including straps, vias, decap…