SoC DV Engineer - Verilog, UVM & Testbench Expert
Listed on 2026-10-06
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Engineering
Test Engineer
Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs.
You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/System Verilog, digital design fundamentals, and scripting (Python/Perl).
For the SoC DV Engineer - Verilog, UVM & Testbench Expert position at Apple Inc., we are reviewing applications now.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Cupertino, CA, United States.
This opportunity is part of our work in IT & Technology.
The advertised compensation is 120..
We aim to respond to suitable candidates as soon as possible.
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