Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Description

Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

We are seeking a Sr. Signal & Power Integrity Engineer to join our hardware team and drive the SI/PI analysis and optimization of advanced packaging solutions for next-generation machine learning and data center ASICs.

In this role, you will own the package-level signal and power integrity strategy - from early architecture trade-offs through design closure, measurement and validation. You'll work at the intersection of IC, package, and board, ensuring our advanced packaging technologies meet dynamic performance, power delivery, and manufacturing targets.

Key job responsibilities

- Lead  package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and silicon  interposer/bridge architectures.

- Design  and optimize package stack-ups: dielectric material selection, impedance  control, layer assignment, and RDL routing for high-speed and power  delivery performance.

- Perform  high-speed channel simulations (S-parameter extraction, time-domain  analysis, eye diagrams) for die-to-die and die-to-board interfaces through  the package.

- Analyze  and optimize the package PDN end-to-end: decoupling strategy, plane  resonance, IR drop, and AC impedance from die bumps through substrate to  board.

- Characterize  and model on-die capacitance, deep trench capacitors (DTCs), and  integrated passive device (IPD) capacitors; evaluate their effectiveness  within the full-stack PDN impedance profile.

- Interface  with SoC die-level PDN teams to align power grid requirements, current  profiles, and decoupling budgets across the chip-package boundary.

- Perform  3D/2.5D EMIR analysis using tools such as Ansys Red Hawk-SC 3

DIC, Cadence  Voltus, or equivalent to validate IR drop and electromigration across  multi-die stacked packages.

- Model  advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias,  and RDL traces for both signal and power paths.

- Apply  equalization techniques (DFE, CTLE, FFE) and evaluate package-level  channel margins for PCIe, UCIe, and custom die-to-die links.

- Perform  clock distribution and jitter analysis at the package level, accounting  for coupling, skew, and return path discontinuities.

- Collaborate  with ASIC design, board design, and packaging/assembly teams to  co-optimize package architecture for electrical performance and  manufacturing yield.

- Identify  and mitigate package manufacturing risks - warpage, via reliability,  impedance variation, and material tolerance impacts on SI/PI.

- Develop  and maintain package SI/PI modeling flows, automation scripts, and design  guidelines.

About the team

Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we're building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.

Diverse Experiences

AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn't followed a traditional path, or includes alternative experiences, don't let it stop you from applying.

About AWS

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Work/Life Balance

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