Senior ASIC Design Engineer

Seeking a Senior ASIC Design Engineer for a high‑growth defense contractor in the Dallas, TX area.

Job Details: Location:
Dallas, TX. Type:
Contract. Salary: $100–$110 per hour.

Work hours:

8:00 AM–4:00 PM.

Education:

Bachelors required.

Benefits: W-2 benefits offered.

• RTL Development: Design and implement complex logic blocks in Verilog/System Verilog for real‑time image processing pipelines.
• Architecture Integration: Integrate SoC components including CPUs, GPUs, and specialized NPU/ISP cores, ensuring seamless communication via AXI/AHB interconnects.
• High‑Speed Design: Develop high‑speed interfaces and implement techniques for managing high‑bandwidth memory traffic (DDR/LPDDR) to support high‑resolution sensor data.
• Performance Optimization: Conduct area, power, and timing analysis to meet the stringent SWaP (Size, Weight, and Power) requirements of tactical electro‑optical systems.
• Verification
  
  Collaboration:
  
  Work closely with the DV team to develop functional coverage models and debug complex issues within a UVM environment.
• Mentorship: Provide technical leadership to junior engineers and contribute to the evolution of internal design standards and IP libraries.

• Minimum 8 years of experience.
• Education:
  
  Bachelors (required).
• Experience level:
  Experienced.

• Circuit Board Design
• Embedded Software Design
• Product Design
• ASIC/FPGA/PLD
• PCB Design
• Verilog
• Design verification
• Validation
• Image Processing

Equal Opportunity

Employer:

Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact