Mixed-Signal Design Verification Engineer | Custom

We are seeking a talented Mixed-Signal Design Verification Engineer with experience in verifying high-speed wireline communications and clock/data paths
. Come be a part of an exciting Top-Level Design Verification (TLDV) Team in the ACS product line, which develops cutting-edge ASSP ICs. The TLDV team builds automated AMS and DMS test benches to verify logical functionality, electrical parameters, performance and reliability of custom high-volume chips. While doing that, we strive for continuous improvement in our tools and methodologies, and believe in teamwork and having fun.

• Execute the pre-silicon verification of complex mixed-signal IC products. Build testbench and automation solutions that are scalable and that support DMS and AMS stimulus and checkers to verify DUT behavior before tapeout.
• Verify high-speed clock and data paths (clock/data recovery, timing, serialization/de-serialization, PLLs, DLLs) such as USB, eUSB, Ser Des and other wireline protocols.
• Verify the design to work according to the datasheet, VVCM, system-level use cases, design-for-test features, and usability from a customer and bench/ATE perspective.
• Work with the design teams and systems teams to provide guidance on Design for Verification architecture during chip development, to triage and close bugs as they arise, and to elaborate and clarify the datasheet and VVCM specifications.
• Be knowledgeable and efficient at using the languages and tools of the trade such as:
  Verilog, System Verilog, Verilog-AMS, Cadence Virtuoso, Spectre, Simvision, text editors, scripting languages, Starfish, CDDS, functional coverage, RTL code coverage, and constrained-random stimulus.
• Evaluate system-level use-cases and re-create these in simulation, including communication with the customer to understand these system cases and to review results with them.
• Create and maintain behavioral models of analog circuits (real-number models, simple logical models, Verilog-AMS electrical or wreal models, or simple schematic models).