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Digital IC Design Engineer | Custom

Job in Dallas, Dallas County, Texas, 75215, USA
Listing for: Texas Instruments
Full Time position
Listed on 2026-06-10
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below

The TI Custom BU is seeking a talented Digital Design Engineer with experience in designing complex mixed-signal devices
. Come be a part of an exciting custom Digital Design Team in the ACS product line with responsibility for planning, architecting, and designing digital and mixed signal circuits for cutting‑edge ASSP ICs for a marquee customer. We strive for continuous improvement in quality, efficiency, and schedule predictability using the latest design tools and methodologies. This role offers the opportunity to be a core member in a team driving flawless execution while finding innovative solutions to customers’ problems through “out of the box thinking” to deliver highly differentiated products.

This individual will:

  • Assist systems team in developing the system spec for the device from a digital and mixed signal point of view.
  • Develop micro architecture documentation from the spec.
  • Drive RTL development and verification (RTL and Gate level)
  • Develop timing constraints and execute logic synthesis.
  • Implement checks to develop high quality netlist for P∧R.
  • Run STA and review design quality from timing point of view.
  • Execute Clock/Reset Domain Crossing Checks (CDC/RDC)
  • Execute Jasper Gold auto-formal verification checks
  • Drive reviews for design and verification.
  • Interact with Analog team to drive chip level requirements for the digital cores.
  • Be proactive in risk assessment and drive solutions to mitigate them.
  • Interact with customers on requirements and refine them.
  • Take an active role in mentoring team members and developing the digital design skill set in the team.
  • Drive RTL design and verification flow improvement strategies.
  • Must take the initiative to drive on‑time first-pass success methodologies.
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