ASIC/FPGA Principal Verification Architect VI
Listed on 2026-02-13
-
Engineering
Systems Engineer, Software Engineer, Electronics Engineer
Description
Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state‑of‑the‑art avionics product in a world class Integrated Product Development environment.
Location: This position does not support teleworking; you will be located near our Lockheed Martin Space facility in:
- Sunnyvale CA
- King of Prussia PA
- Denver CO or Highlands Ranch CO
- Titusville FL
You will work a flexible 9x80 schedule in the office full‑time.
About UsBy bringing together people that use their passion for purposeful innovation, at Lockheed Martin we keep people safe and solve the world’s most complex challenges. Our people are some of the greatest minds in the industry and truly make Lockheed Martin a great place to work. With our employees as our priority, we provide diverse career opportunities designed to propel development and boost agility.
Our flexible schedules, competitive pay, and comprehensive benefits enable our employees to live a healthy, fulfilling life at and outside of work.
We are building the best SOC team in the world at Lockheed Martin Space’s Silicon Solutions team and seeking a future‑looking Principal Verification Architect who is able to case and realize a compelling vision which will improve speed and efficiency of the verification / validation of ASICs, FPGAs, and SOCs.
Key activities you will accomplish in this role- Serve as the Principal Subject Matter Expert (SME) regarding verification and validation for the department.
- Develop roadmaps and processes related to verification and validation of complex devices.
- Develop and promote strategies and techniques that scale from low‑level to system‑level to improve cost and timelines.
- Mentor others in the best practices of verification and validation.
- Continuously assess new tools and methodologies related to verification and validation, presenting findings, making recommendations, and training others.
- Work closely with design, verification and software teams to develop cohesive solutions.
- Develop business cases that support verification and validation improvements.
- Support all aspects of ASIC, FPGA, and SOC development, including architecture, design, and analysis.
- Support technical reviews, and present to internal and external stakeholders.
- Experience in verification of FPGA and ASIC devices.
- 12+ years of professional experience.
- Willing and able to obtain and maintain a DoD Top Secret clearance
, thus you are a US Citizen
.
- Experience in verification of FPGA and ASIC devices utilizing modern verification methodologies such as UVM, Formal, Emulation, lab and/or proprietary / lesser‑known methods.
- Experience architecting advanced testing environments for complex custom or fixed SoC's, such as AMD Versal, and multiple chip designs, leveraging multiple verification strategies as appropriate.
- Experience leading projects of multiple engineers, preferably cross‑functional teams that include software and circuit ware developers; and managing schedules, prioritizing work and actively communicating with internal or external stakeholders.
- Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
- Willing and able to obtain and maintain a government‑sponsored security clearance, thus US Citizenship is required for this position.
- Experience in formal verification methodologies (property checking, connectivity checking, FuSa, coverage analysis, etc.).
- Experience in hardware emulation (ZeBu, Palladium, etc.).
- Experience working closely with SoC design and cross functional teams to refine requirements and fully define the verification plan for complex FPGA's and ASIC's.
- Experience in driving process advancement and program reviews.
- HDL programming experience with VHDL, System Verilog, and/or Verilog.
- Experience developing test cases based off given requirements.
- Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
- Experience identifying and implementing necessary test exclusions.
- Experience analyzing coverage results generating coverage…
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