ASIC Engineer, Performance Architecture and Modeling
Job in
Dover, Kent County, Delaware, 19904, USA
Listing for:
Meta
Full Time
position
Listed on 2026-09-01
Job specializations:
-
Engineering
Systems Engineer, Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 178000 - 250000 USD Yearly
USD
178000.00
250000.00
YEAR
Job Description & How to Apply Below
Summary:
Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.
ASIC
Engineer, Performance Architecture and Modeling Responsibilities:
Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environmentsDrive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisionsDevelop and validate pre-silicon performance models that accurately predict post-silicon behavior for data center workloadsDevelop low-level workloads and kernels for machine learning training and inference applicationsEstablish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipelineCollaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specificationsPartner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristicsLead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadershipDefine long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investmentsMentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practicesIdentify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibrationMinimum Qualifications:Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience8+ years of experience in ASIC design, silicon engineering, or a related technical field5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designsProficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis toolsExperience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems including processors, memory subsystems, or high-speed interconnectsExperience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom siliconExperience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teamsExperience with assembly programming languages, and compiler technologiesPreferred Qualifications:Experience with hardware description languages (e.g., System Verilog, VHDL) and simulation environments used in ASIC development flowsExperience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designsFamiliarity with post-silicon performance validation and model-to-hardware correlation methodologiesExperience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysisExperience with GPU, machine learning, multi-threaded programming paradigmExperience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimizationPublic Compensation:
$178,000/year to $250,000/year + bonus + equity + benefits
Industry:
Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affinitive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.
We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with…
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