Principal Layout Design Engineer

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high‑performance, energy‑efficient AI compute.

As a key member of the layout team, you will be responsible for delivering clean layouts that meet LVS, DRC, ERC, EM, and IR requirements. Your role will involve close collaboration with various teams to ensure seamless full‑chip integration and high‑quality design implementation.

• Collaborate with the Place & Route (P&R) team to resolve full‑chip integration issues.
• Develop and improve methodologies to simplify custom macro integration into the P&R flow.
• Floorplan and build out cells, blocks, and macros efficiently.
• Understand, create, and debug LEF files to support design processes.
• Design complex layouts for both analog and digital circuits using deep submicron technologies.
• Analyze and interpret LVS, DRC, ERC, EM, and IR results to identify and resolve issues.
• Identify schematic or layout problems and work closely with engineering teams to address them.
• Work on multiple projects across different technologies simultaneously.
• Learn and effectively utilize Ampere’s in‑house design tools.
• Coordinate with circuit engineers located in different regions and time zones.
• Support and assist during tape‑out phases to ensure successful project completion.
• Contribute ideas as an integral part of a small, collaborative team.
• Coach and train junior engineers to foster skill development within the team.

• Minimum of 8 years’ experience in custom layout design.
• Current hands‑on experience with 3nm technology is essential.
• High proficiency in laying out custom digital components such as SRAM, register files, and standard cells.
• Strong skills in designing custom analog blocks including amplifiers and resistor ladders.
• Expertise in laying out and balancing custom clock H‑trees for full‑chip designs.
• Experience with full‑chip integration of custom IP alongside P&R teams.
• Solid knowledge of Design for Manufacturability (DFM), hierarchical layout techniques, device matching, and low‑parasitic layout practices.
• Good understanding of Electromigration (EM) and IR drop analysis.
• Proficient with Cadence XL/GXL/EXL and Mentor Graphics Calibre tools.
• Familiarity with Cadence Innovus is a plus.
• Experience with Totem tools for EM/IR analysis is advantageous.
• Programming skills are a plus but not required.
• Excellent communication skills with the ability to collaborate effectively across multiple locations and time zones.
• Bachelor’s degree & 8 years of related experience; or master’s degree & 6 years; or PhD & 3 years.

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long‑term incentive, and comprehensive benefits.

The full base pay range for this role is between $182,000 and $273,000, except in the San Francisco Bay Area where the range is between $195,000 and $292,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401(k) retirement plan.
• Unlimited flextime and 10+ paid holidays.
• A variety of healthy snacks, energizing espresso, and refreshing drinks.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.