Senior ASIC Physical Design Engineer

Physical Design Engineer

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Tweaker/Prime Time.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Minimum Qualifications:

• Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience, or Master's degree in Electrical or Computer engineering and 4+ years of ASIC relevant experience, or PhD in Electrical or Computer engineering + 1 year of ASIC relevant experience
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

Preferred Qualifications:

• Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.
• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience with custom clock (H-Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts