Senior ASIC Verification Engineer

Senior ASIC Verification Engineer

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from our Durham office. US Citizenship Preferred

You will architect, design, and implement complex networking ASICs. You will create chip‑level and block‑level architecture and micro‑architecture, write high‑quality RTL, and work closely with verification and physical design teams to deliver clean, efficient, and high‑performance silicon.

• Define ASIC architecture for networking chips, including data paths, packet processing, control logic, memory structures, and interfaces.
• Develop detailed micro‑architecture for complex blocks and ensure they meet functional and performance goals.
• Write clear, efficient, synthesizable RTL (System Verilog/Verilog) for the designed blocks. Create assertions and assist in functional coverage
• Work closely with verification engineers to ensure the RTL is fully tested, bug‑free, and meets all functional requirements.
• Provide guidance to the verification team on test plans, coverage goals, corner cases, and expected behavior.
• Collaborate with physical design engineers to ensure the design meets timing, area, and power targets.
• Review synthesis, timing, and power reports, and update RTL or micro‑architecture as needed.
• Participate in design reviews, provide clear feedback, and ensure compliance with design guidelines.
• Support integration and debug during simulation, emulation and silicon bring‑up.
• Identify technical risks early and propose simple, effective solutions.

• Bachelor's, Master's or PHD degree in Electrical Engineering, Computer Science or Computer Engineering or equivalent.
• Typically, 8+ years' experience

• Strong understanding of ASIC architecture and micro‑architecture.
• Strong background in networking ASICs (switching, routing, packet processing, or similar preferred).
• Expert in RTL coding in Verilog or System Verilog, assertions and functional coverage
• Strong knowledge of digital design fundamentals, pipelining, clocking, resets, FIFOs, arbiters, and data path design.
• Experience working with verification teams and understanding of UVM‑based flows.
• Experience working with physical design teams and understanding constraints for timing, power, and area.
• Familiarity with EDA tools for simulation, synthesis, lint, CDC, timing analysis, and power analysis.
• Good written and verbal communication skills.
• History of technical contributions, innovation, or mentorship.

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America:
Annual Salary USD 135, in North Carolina The listed salary range reflects base salary. Variable incentives may also be offered.