Senior Layout Designer – Pathfinding

Responsibilities

• Develop and prepare multi-dimensional layouts
• Provide detailed drawings of semiconductor devices from schematics
• Verify data integrity
• Communicate effectively with other functional groups across global sites
• Organize and prioritize logistics and resource allocations
• Contribute to group management and technical innovation
• Effectively mentor junior team members
• Contribute to the improvement of layout efficiency through automation and new methodologies
• Lead, plan, and deliver major blocks and product revisions

• AS or Bachelor's in Electronics, Electrical Engineering, or a related field
• 3 years of direct experience in semiconductor layout design
• Deep working knowledge of EDA tools (i.e., Cadence Virtuoso, Synopsys, Calibre)
• Strong ability to debug problems through root‑cause analysis
• Skilled in developing and applying custom layout, floor‑planning, signal‑planning, and power‑planning methodologies
• Strong verbal and written communication skills
• In‑depth understanding of design rules and delivering quality layouts
• Strong physical verification analysis and debugging skills

Demonstrates expertise in semiconductor layout design, utilizing EDA tools for effective debugging and verification. Capable of mentoring team members while driving innovation and efficiency in layout methodologies.

• Cadence Virtuoso
• Synopsys
• Calibre