FPGA Design Engineer

FPGA Design Engineer

We are seeking an experienced FPGA Design Engineer to support the development, optimization, and deployment of digital signal processing (DSP) functions on FPGA platforms. As a member of our engineering team, you will be responsible for designing, implementing, and validating high‑performance digital systems that efficiently translate complex algorithms into synthesizable hardware for RF applications. This role involves contributing to advanced DSP workflows, enhancing real‑time processing capabilities, and advancing our algorithm‑to‑hardware development pipeline.

• Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA tool chains.
• Develop, optimize, and implement DSP algorithms—including filtering, detection, synchronization, modulation and demodulation, transforms, and feature‑extraction—into high‑throughput, resource‑efficient hardware blocks.
• Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.
• Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints.
• Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.
• Develop reusable hardware IP blocks, enabling scalable DSP pipelines and accelerating future development.
• Maintain documentation, including design notes, block diagrams, interface definitions, user guides, and workflow references.
• Contribute to innovation, identifying new techniques and technologies that improve FPGA development efficiency, DSP performance, or overall system capability.

• 3+ years of experience developing FPGA or SDR solutions for DSP or RF applications, including prototyping DSP algorithms in hardware such as filtering, detection, synchronization, modulation, demodulation, transforms, and feature extraction.
• Experience designing FPGA solutions using Verilog, VHDL, System Verilog, or HLS and working with Xilinx, Vitis, or Vivado development ecosystems.
• Experience applying FPGA toolchain workflows, including simulation, synthesis, fitting, timing analysis, implementation, and hardware debug.
• Experience integrating FPGA designs with embedded hardware systems or FPGA‑connected RF front ends and adapting vendor RF transceiver reference designs, such as RTL, IP cores, or drivers, to evaluation boards or custom platforms.
• Experience using Python, C++, or MATLAB for modeling DSP algorithms, as well as scripting with Python, Bash, or Tcl for automation workflows.
• Knowledge of embedded systems concepts, including memory interfaces, buses, soft‑core CPUs, and high‑speed digital interfaces such as AXI‑Stream, AXI‑Lite, DMA, and custom streaming buses.
• Knowledge of Linux or UNIX development environments and digital design fundamentals, including streaming architectures, pipelining, buffering, and Data Path timing.
• Ability to read hardware schematics, operate lab equipment including logic analyzers, oscilloscopes, and spectrum analyzers, and collaborate in multidisciplinary teams while also working independently on complex engineering tasks.
• TS/SCI clearance required.
• Bachelor’s degree in Electrical Engineering or Computer Engineering.

• Experience building DSP IP libraries for reuse across modem or signal‑processing applications.
• Experience with System Verilog or UVM for verification.
• Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation.
• Experience with C/C++ or Rust for embedded or performance‑critical firmware.
• Experience with GPU acceleration, parallel computing, or high‑bandwidth data processing.
• Experience gathering requirements, shaping development roadmaps, or supporting Agile workflows.
• Knowledge of modern agentic engineering workflows, such as AI‑driven automation for FPGA design, simulation, synthesis, or testing.
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Applicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information; TS/SCI clearance is required.

The projected compensation range for this position is $69,400.00–$ (annualized USD). Additional benefits include health, life, disability, financial, and retirement benefits, paid leave, professional development, tuition assistance, work‑life programs, and dependent care. The posting will close within 90 days from the posting date.

All qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local, or international law.