Static Timing Analysis; STA Engineer Lead or Senior

Position

Static Timing Analysis (STA) Engineer – (Lead or Senior)

Company:
Boeing Space, Intelligence & Weapons Systems

Location:

El Segundo, CA – 100% onsite

• Perform pre‑layout and post‑layout timing analysis for ASICs, SoCs, and FPGAs.
• Converge STA throughout the ASIC cycle (RTL to GDS), finding solutions for intricate timing paths (digital, analog, and mixed‑signal).
• Facilitate STA methodology in collaboration with other STA leaders.
• Generate tool‑independent timing constraints for synthesis, place & route, and static timing analysis, including primary input setup/hold, output required arrival time (RAT), and skew constraints.
• Extract timing information from circuit analysis and develop primary constraints.
• Program using Python, TCL, Perl, Unix shell, and related scripting languages.
• Assist in training new engineers.

• Bachelor of Science in Engineering (Electrical, Mechanical, Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or a non‑U.S. equivalent qualification directly related to the work statement.
• 5 years of experience with timing closure on ASICs and FPGAs.
• Experience with multiple ASICs/FPGAs sign‑offs and at least one ASIC tape‑out.
• Good understanding of RTL to GDS flow.
• Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis.
• Ability to work with large physical design teams to achieve timing convergence.

• Lead, Level5: 15+ years of related work experience or an equivalent combination of education and experience.
• 10+ years of experience with timing closure on ASICs and FPGAs.
• Completed multiple first‑pass successful ASIC tape‑outs, dealing with intricacies such as cross‑clock domain and asynchronous crossing.
• Experience using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime) and familiarity with Synopsys Fusion Compiler, Formality, and other relevant tools (e.g., TCM, Fishtail).
• Experience with Synopsys physical design AI tools.
• Leadership of static timing closure and training of new hires.
• Familiarity with space‑based design techniques and radiation mitigation.
• Understanding of design for testability (DFT) and its impact on timing.
• Proficiency with multiple scripting languages (Python, C/C++, shell, TCL).
• Capability to handle timing closure on multiple designs simultaneously.

• Lead, Level4:
  Typically a bachelor’s degree plus 9+ years of related work experience (or equivalent education and experience).
• Senior, Level5:
  Typically a bachelor’s degree plus 14+ years of related work experience (or equivalent education and experience).
• ABET accreditation preferred, though not required.

• Position is 100% onsite in El Segundo, CA.
• Optional 9/80 schedule rotation (9‑hour shifts, 8 days per pay period, alternate Fridays off).
• Travel up to 10% of time, domestically and/or internationally.
• U.S. citizenship required; ability to obtain a U.S. security clearance (interim or final U.S. Secret, Top Secret, or Top‑Secret SCI).
• Relocation assistance provided based on eligibility.

Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status, or any other characteristic protected by law. Boeing EEO Policy:
Request an accommodation. Applicant privacy is protected. Boeing participates in E‑Verify. The law requires that you have the right to work in the United States.

Shift: 1st shift (United States of America).

• Lead (Level4): $146,200 – $197,800.
• Senior (Level5): $176,800 – $239,200.

Visa sponsorship not offered. The position is not contingent upon program award and does not require a recruitment fraud verification.