RTL Engineer

About Us

Micro Vision is a global leader in innovative perception solutions, with offices in the U.S. and Germany. The company focuses on developing and supplying integrated lidar hardware and perception software to enhance safety and automation across various industrial applications, including robotics, automated warehouses, agriculture, and autonomous systems. Its core technology, originally designed for the automotive industry, supports advanced driver‑assist systems and autonomous driving and extends to military segment products such as semi‑ and fully autonomous airborne and terrestrial sensor systems.

The firm’s solid‑state lidar technologies, including MEMS‑based long‑range lidar and flash‑based short‑range lidar, integrated with onboard perception software, enable safe mobility at high speed.

Micro Vision has an immediate opportunity for a Staff RTL Engineer. As a key member of the Digital Design Engineering team, you will collaborate with various technical teams to design and bring to market a defining Automotive LiDAR product. The right candidate will be a highly motivated FPGA/RTL engineer with breadth of understanding in FPGA design and best practices, including detailed design, System Verilog coding, modeling, simulation, verification, integration and test.

• Derive FPGA requirements based on system requirements then create FPGA architecture to fulfill those requirements
• Design, implement and test Register‑Transfer Level (RTL) features and components guided by system architecture and requirements
• Own the detailed design of assigned firmware components and subsystem functionality
• Document test and implementation plans at unit and system levels and execute on them
• Work with other teams to integrate developed features into system hardware
• Support bringing up RTL features developed by the team
• Coach and mentor junior members of RTL and integration teams to complete tasks
• Participate in the full software development life cycle (SDLC) flow including peer reviews of requirements, architecture, design, and code implementations within an approved ASPICE development flow

• Knowledge of System Verilog, Verilog, and Python programming languages
• Proficiency in FPGA design methodologies from state machine design to DSP implementation
• Experience closing timing in FPGA designs
• Mapping algorithms to FPGA‑appropriate logic implementations
• Expertise integrating and bringing up features in hardware
• Ability to work well in a fast‑moving and complex environment
• Independently driven to complete project tasks
• Experience with configuration management and change control concepts and tools (Git, Subversion, Jira, etc.)
• Experience working with functional requirements and defining requirement‑based tests
• Experience performing HDL synthesis and simulation (e.g., VCS, Synplify, etc.)
• Experience with design analyses (timing, lint, clock domain crossings, code coverage, etc.) and IP compliance strategies
• Experience designing portable, scalable test benches
• Experience with UVM/OVM – constrained random testing
• Familiarity with hierarchical simulation and verification frameworks
• Experience with inter‑system communication protocols (I2C, UART, SPI, etc.)
• Familiarity with microcontroller peripherals including ADCs, DACs, Flash, EEPROM, timers, and watchdogs
• Working knowledge of data structures and algorithm fundamentals
• Working knowledge of digital and analog electronics

• Knowledgeable of control systems and digital signal processing fundamentals
• Proficient in embedded software systems developed in C/C++
• Hands‑on experience with High‑Level Synthesis (HLS)
• Excellent scripting and automation skills (Bash, Python, Make/CMake, TCL)
• Extensive project experience working on embedded laser applications including LiDAR
• Safety‑critical industry experience (FIT analysis, etc.)
• Working knowledge of various computing architectures beyond FPGAs, such as DSPs, GPUs, or MCUs, and their associated hardware computing platforms used to program them
• Experience with ASIC design and migration from FPGA prototypes to production ASICs