SOC IP Methodology Engineer - Custom SOC

Job Requisition

Job Category:
Engineering

Time Type:
Full time

• Develop and optimize semi-custom RTL to GDS methodologies, working with internal and external collaborators and IP vendors on SOC/IP requirements to drive technology alignment.
• Act as a hands‑on domain expert, traversing from synthesis to final design closure (timing and layout) using latest EDA technologies.
• Collaborate with customers on SOC/IP development processes, IP quality and handoff requirements for QA, smooth integration, and high‑quality analysis flows.
• Drive, review, and cultivate development processes to assure top quality work to and from IP customers and SOC engineers.
• Lead technical design reviews, ensure defined processes are followed, identify and mitigate risks, and continually improve development processes with innovative tools and procedures.
• Be responsible for results/handoffs to and from customers, methodology solutions, and schedule plans.
• Drive early PPA on customer IP and conduct what‑if experiments to support KPI targets, analyze and solve critical issues.
• Work with internal and external collaborators to carry out floorplan experiments for area estimation and trade‑off evaluation.
• Coordinate with Nvidia PD design methodology team to develop the best methodologies for integrating external customer IP.
• Collaborate with external ASIC companies if outsourcing parts of Nvidia’s design.

• Master’s degree with 8+ years (or BS/experience 10+) of relevant experience.
• Extensive leadership experience as a methodology and technical expert in physical design, working with internal and external partners.
• Experience in a SOC development and customer‑focused environment with excellent interpersonal skills.
• Experience handling complex IP ecosystems involving both internal and external partners; exposure to IP‑XACT or similar infrastructure is a plus.
• Proven hands‑on experience with RTL‑to‑GDSII tool flows and EDA vendor tools such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT‑SI, Tempus, Redhawk).
• Understanding of the full flow (including DFT, BIST) to integrate customer and third‑party IP and drive program alignment.
• Proven ability to optimize methodologies and flows for high productivity, design optimization, and innovation.
• Strong background in synthesis, CTS, power optimization, placement and route methods, and timing convergence for high‑performance designs (CPU, GPU, machine‑learning IP).
• Strong scripting skills involving Python, Perl, and Tcl; excellent soft skills.
• RTL2
  
  GDS experience with high‑performance ARM cores, Ser Des, DDR, GPU, and machine‑learning IP is a plus.

The base salary will be determined based on location, experience, and comparable positions. Salary ranges are $168,000–$264,500 USD for Level 4 and $196,000–$310,500 USD for Level 5. In addition, you will be eligible for equity and benefits.

NVIDIA is committed to fostering an inclusive work environment and is an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.