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Senior ASIC PD Engineer — Cache Coherent Interconnects
Job in
Eugene, Lane County, Oregon, 97403, USA
Listed on 2026-08-22
Listing for:
NVIDIA AI
Full Time
position Listed on 2026-08-22
Job specializations:
-
Engineering
Electronics Engineer
Job Description & How to Apply Below
NVIDIA is seeking engineers for the CPU Cache Coherent Interconnects Design Team to drive physical design of the on-chip interconnect network and last-level caches, with responsibilities across synthesis, timing closure, and collaboration with logic teams on micro-architecture feasibility.
The role requires a Master’s degree and 5+ years in high-performance semiconductor design, with strong Verilog expertise and experience in RTL, DFT, and ECO.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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