Design Verification Engineer; PCIe Fastwater Staffing

We are looking for an experienced Design Verification Engineer (Contract) to join our team and support ongoing PCIe verification efforts. This role involves hands‑on test bench development, debugging, and compliance‑focused verification using Avery PCIe VIP
.

• Develop, enhance, and maintain System Verilog/UVM test benches
• Create directed, random, and compliance‑driven test scenarios
• Integrate and work extensively with Avery PCIe VIP
• Debug simulation failures and analyze PCIe protocol violations
• Contribute to coverage closure and verification signoff

• 5+ years of experience in Design Verification
• Strong proficiency in System Verilog and UVM
• Hands‑on experience using Avery PCIe VIP (mandatory)
• Solid understanding of the PCIe protocol (Gen6 preferred)

• Experience with Avery Compliance test suite
• Familiarity with PCIe Physical and Data link layer protocol
• Knowledge of Root complex and Endpoint
• Understanding of scoreboards, monitors, and verification architecture design

• Location:
  
  Remote / On‑site (Preferred)
• Start date:
  
  Immediate
• Hourly/weekly rate: DOE (Depending on Experience)