Senior RTL Design Engineer, CPU

Senior RTL Design Engineer, CPU Link

Driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Eight years of experience in high-performance CPU or AI accelerator logic design, RTL design, or integration, including microarchitecture definition and PPA optimizations. Experience in CPU, and cache subsystem integration with SOCs.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering or Computer Science. Experience with modern processor microarchitecture and related technologies and algorithms, through industry experience. Experience with ARM instruction set architecture. Experience with SOC integration, design and architecture. Equipped with AI usage experience. Knowledge with a HDL language, front-end design methodology, and programming languages, such as C, C++, and Python.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Participate in developing CPU or AI accelerator design and deliveries into SOC. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU. Deliver designs meeting Power, Performance, and Area (PPA) and functional goals. Be familiar with modern techniques, interpret the techniques into design constructs, and languages in order to participate in SOC integration effort. Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.