Principal HIG ESD and Latch-up Engineer- HBM - TPG

Responsibilities

• Define and own chip‑level and IP‑level ESD and latch‑up strategies for HBM DRAM, base die, I/O, TSVs, and die‑to‑die interfaces
• Establish ESD and latch‑up requirements, targets, and sign‑off criteria aligned with JEDEC/ESDA standards
• Enable ESD protection circuits and latch‑up safe layout practices across designs and technologies
• Lead silicon validation, failure analysis, and correlation of pre‑silicon assumptions to silicon results
• Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams

• Master’s degree or Ph.D. in Electrical Engineering or equivalent industry experience
• Strong fundamentals in ESD physics, latch‑up mechanisms, and advanced CMOS devices
• Hands‑on experience with ESD protection circuits and latch‑up prevention techniques
• Familiarity with JEDEC and ESDA standards, including HBM, CDM, and JESD
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• Experience supporting ESD and latch‑up sign‑off for advanced DRAM or HBM products
• Knowledge of SCR‑based clamps, distributed ESD networks, and rail‑based strategies
• Experience working directly with foundry ESD and latch‑up teams
• Proven ability to mentor engineers and influence design methodology across teams

Systems Design Engineer 5

TBD

$ – $ a year (base salary). Additional compensation may include bonuses, equity, and benefits.

Benefits include medical, dental, vision plans, income protection, paid family leave, paid time‑off, and paid holidays. See the Benefits Guide posted on Micron Technology, Inc.

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.