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Senior Member of Technical Staff, AI-optimized Memory SoC Microarchitect

Job in Folsom, Sacramento County, California, 95630, USA
Listing for: 1000 Micron Technology, Inc.
Full Time position
Listed on 2026-05-31
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below

Senior Member of Technical Staff – AI‑Optimized Architecture
Micron Technology invites an experienced hardware architect to lead SoC microarchitecture design for high‑performance, AI‑oriented memory solutions. The role focuses on defining and driving the architectural strategy, trade‑offs, and detailed implementations for tightly coupled memory systems that support demanding AI workloads.

Responsibilities
  • Define SoC microarchitecture, including clocking architectures, power sequencing, power delivery, and signal interfaces.
  • Own and drive estimates, optimizations, and trade‑offs for full‑chip timing, area, performance, power, and energy.
  • Define and analyze on‑die power delivery networks (PDN), IR‑drop budgets, and power grid topologies.
  • Analyze full‑chip thermal implications, identify power hotspots, and propose mitigation strategies.
  • Define DFT architectures (e.g., scan chain topology) and set verification requirements.
  • Define SoC floor plans in collaboration with physical designers.
  • Compose and maintain clear SoC microarchitecture documentation.
Preferred Qualifications
  • Strong foundation in analog and digital circuit design, applied to IP interface requirements, power delivery behavior, and clocking constraints.
  • Experience with RTL design and development of microarchitecture specifications.
  • Familiarity with chip‑level thermal analysis and power‑hotspot mitigation strategies.
  • Proficiency in reasoning about finite state machines, interconnects, and frequency vs. energy/power trade‑offs.
  • Experience with synthesis, static timing analysis, and relevant EDA toolsets (Prime Power, Prime Shield, Redhawk, ICC2).
Minimum Qualifications
  • Experience with advanced packaging building blocks and techniques.
  • Experience with high‑performance and efficient stacked architectures.
  • Ability to influence decisions through data‑driven analysis and clear communication.
  • A Master’s or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
  • 8+ years of proven industry experience delivering silicon‑demonstrated SoC hardware designs.
Salary & Benefits
  • U.S. base salary range: $ – $ per year.
  • Additional compensation may include bonuses, equity, and a comprehensive benefits package.
  • Benefits include medical, dental, vision, income protection, paid family leave, paid time off, and paid holidays.

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.

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Position Requirements
10+ Years work experience
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