Senior Member of Technical Staff, AI-optimized Memory SoC Microarchitect

Job Overview

Req  Senior Member of Technical Staff, AI-optimized Memory SoC Microarchitect

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next‑generation, high‑performance memory solutions for AI. In Micron’s AI‑optimized Memory Architecture organization, we partner closely with customers to design and deliver memory solutions purpose‑built for emerging AI systems and applications!

As a Senior Member of Technical Staff in the AI‑optimized Architecture team, you will drive the definition of SoC microarchitecture of tightly coupled, high‑performance memory for AI workloads. Apply expert knowledge to analyze micro‑architectural SoC trade‑offs in close collaboration with peer architecture, design, and packaging teams. Drive microarchitecture and early SoC design activities, including definition of IP interfaces (e.g., signals, power delivery), clocking, power sequencing, design‑for‑test, floor planning, and specification development.

• Define SoC microarchitecture, including clocking architectures, power sequencing, power delivery, and signal interfaces.
• Own and drive estimates of and optimizations for full-chip timing, area, performance, power, and energy.
• Define and analyze on‑die power delivery networks (PDN), including IR drop budgets and power grid topologies.
• Analyze full-chip thermal implications, including power hotspot identification and mitigation.
• Define DFT architectures (e.g., scan chain topology), and set verification requirements.
• Define SoC floor plans in collaboration with physical designers.
• Compose and maintain clear SoC microarchitecture documentation.

• Strong foundation in analog and digital circuit design, applied to IP interface requirements, power delivery behavior, and clocking constraints.
• Experience with RTL design and developing/maintaining microarchitecture specifications.
• Familiarity with chip‑level thermal analysis and power hotspot mitigation strategies.
• Experience reasoning about finite state machines, interconnects, and frequency vs. energy/power tradeoffs.
• Experience with synthesis, static timing analysis, and relevant EDA toolsets:
  Prime Power, Prime Shield, Redhawk, and ICC
  2.

• Experience with advanced packaging building blocks and techniques.
• Experience with high performance and efficiency stacked architectures.
• Ability to influence decisions through data‑driven analysis and clear communication.
• A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• 8+ years of proven industry experience delivering silicon‑demonstrated SoC hardware designs.

Systems Design Engineering SMTS

TBD

The base salary range for this full‑time position is $191,000–$334,000 per year. Additional compensation may include benefits, bonuses and equity.

Benefits include medical, dental, vision coverage, paid time‑off, paid holidays, family leave and health‑related coverage for employees and eligible dependents.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.