Senior Design Verification Engineer- Mixed Signal IP

Job Details

Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.

We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

• Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
• Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Maintains and improves existing functional verification infrastructure and methodology.

• BS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 8+ years of relevant industry experience in Design verification, System Verilog and OVM/UVM.
• MS degree in same field with 6+ years of relevant industry experience.
• PhD in same field with 4+ years of relevant industry experience.
• Experienced in validation flow from test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS.
• Knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols.
• Experience in scripting skills in Python/Perl.
• Exposure to Formal Property Verification and Git/Perforce/CVS version control.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary

Location:

Folsom, California, USA

Additional Locations:
Santa Clara, California, USA

• Competitive pay
• Stock bonuses
• Health, retirement, and vacation benefits
• Hybrid work model allowing split time between on-site and off-site work

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.