Formal Verification Engineer - CPU Core

Job Responsibilities

During this role you will exhaustively verify the architecture and micro-architecture changes implemented in the CPU via dynamic and formal verification methods. Responsibilities include writing verification test plans, writing tests to execute those plans, and developing pre‑silicon verification collateral such as behavioral checkers, coverage monitors, test generators, or score‑boards to enable test plan execution. On the formal front you may own formal verification of a micro‑architecture block or a significant portion of the Big Core CPU, contribute to the micro‑architecture specification, define a formal verification strategy, lead ROI analysis, and recommend the appropriate use of formal versus dynamic validation techniques.

You will debug failing tests, collaborate with designers and architects to resolve bugs, anticipate failure modes, write rigorous test content to stress the design, analyze coverage gaps, devise strategies to fill coverage holes, and work with global RTL, Arch DV and Formal teams to define verification strategy, planning, execution, and methodology.

• Strong problem solving
• Tolerance of ambiguity

• Bachelors degree in Computer Engineering, Electrical Engineering or related STEM field AND 2+ years of relevant work experience, OR Masters degree in same field AND 1 year of relevant work experience
• 1+ years’ experience with in‑depth computer architecture knowledge (out of order processor execution, memory hierarchy, memory management)
• Experience with hardware modeling language such as Verilog, VHDL, or System Verilog and industry‑standard logic simulation tools
• Experience with assertion writing, checker development, coverage analysis, failure debugging, root cause analysis
• Programming proficiency in at least one language (C/C++, Java, Specman E, etc.) and scripting languages (Perl, Python, Ruby, TCL)
• Intel or industry experience in pre‑silicon verification of CPU cores (technical ownership in CPUs)
• Industry‑standard formal verification tools such as Jasper Gold, IFV, Questa Formal, VC Formal

• Knowledge of Intel Architecture ISA and system architecture, x86 assembly language
• Pre/Post‑silicon debug and analysis
• Research publications, patent filings, or evidence of personal technical innovation in validation methodology advancement
• Experience applying sequential equivalence checking in complex micro‑architectures
• Experience with formal abstractions and complexity reduction techniques

Our total rewards package includes competitive pay, stock bonuses, health, retirement, vacation, and other benefits. Annual salary range: $ - $ USD.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

US, California, Folsom (Hybrid work model).