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Sr. Member Technical Staff - ESD and Latch-Up - HBM

Job in Folsom, Sacramento County, California, 95630, USA
Listing for: Micron Technology, Inc
Full Time position
Listed on 2026-07-09
Job specializations:
  • Engineering
    Test Engineer, Systems Engineer, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 177000 - 334000 USD Yearly USD 177000.00 334000.00 YEAR
Job Description & How to Apply Below

Sr. Member Technical Staff – ESD and Latch‑Up – HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We define ESD and latch‑up architecture for next‑generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high‑performance memory!

As an SMTS/DMTS HBM ESD/Latch‑Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system‑level ESD challenges.

Responsibilities
  • Define end‑to‑end ESD and latch‑up architecture across base die, DRAM die, and interconnects
  • Develop protection strategies for high‑speed I/O, TSV interfaces, and advanced packaging
  • Establish ESD/LUP standards, rule decks, and sign‑off criteria
  • Drive correlation between design assumptions, silicon validation, and field reliability
  • Partner with foundry and packaging teams on system‑level ESD challenges
Minimum Qualifications
  • MS or PhD in Electrical Engineering or related field, or equivalent practical experience
  • 10+ years of experience in ESD and latch‑up design and reliability
  • Expertise in advanced CMOS technologies such as FinFET or GAA
  • Experience with 3D IC, TSV, or die‑to‑die interfaces
Preferred Qualifications
  • Experience defining architecture across multi‑die or stacked memory systems
  • Background in ESD device or circuit design
  • Experience developing PDK collateral or ESD rule decks
  • Experience debugging silicon failures related to ESD or latch‑up
  • Demonstrated technical leadership across cross‑functional teams
Salary

$177,000 – $334,000 per year (base salary). Additional compensation may include benefits, bonuses and equity.

EEO Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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