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Design Verification Architect

Job in Folsom, Sacramento County, California, 95630, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-07-16
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 180000 USD Yearly USD 140000.00 180000.00 YEAR
Job Description & How to Apply Below

Job Overview

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner. Architects the test benches and develops universal verification methodology (UVM) or formal based verification approaches. Integrates the block testbench in chip-level UVM environment and verifies integration. Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications.

Enables interaction with analoga and digital teams and supports postsilicon validation activities. Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure. Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage.

Responsibilities

Architect test benches, develop verification methodology, integrate block test benches into chip-level UVM environment, verify integration, create test strategy and plans, interact with analog/digital teams, support postsilicon validation, collaborate on random test generation plans, run functional simulations, conduct failure and coverage analysis, develop security validation strategy and infrastructure.

Minimum Qualifications
  • Bachelor's degree in Electronics, Computer Engineering, or related field and at least 6+ years of experience
  • or a Master's degree in the mentioned fields with 4+ years of experience in silicon design development, frontend validation methodologies, simulation environment development (testbench, checker), and simulation/emulation debugging
  • Proficiency in functional and code coverage closures
  • Expertise in hardware simulation and validation tools, with strong technical proficiency in C/C++/Python and System Verilog
  • Familiarity with IP validation tools, processes, and protocols
Preferred Qualifications
  • Experience with OVM/UVM-based test benches and formal verification tools
  • Deep knowledge of graphics architecture and designs, with an understanding of microarchitectural features
  • Strong team collaboration skills, problem-solving ability, and attention to detail
EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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