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RTL Design Engineer: SystemVerilog & Power Optimizations
Job in
Folsom, Sacramento County, California, 95630, USA
Listed on 2026-07-20
Listing for:
Jobtailor
Full Time
position Listed on 2026-07-20
Job specializations:
-
Engineering
Electronics Engineer, Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Jobtailor is seeking an RTL design engineer to develop logic for IP blocks using System Verilog and Verilog, optimize for power and performance, and help shape microarchitecture features. You will collaborate with verification teams to ensure robust design validation and support SoC customers with integration and handoff.
The role emphasizes clock gating, UPF low‑power coding, and cross‑functional teamwork to deliver high-quality IP blocks and maintain design quality standards.
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