Intern - HBM SoC RTL Design Engineer

Our Vision

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next-generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high-performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Collaborate with SoC architects to translate architectural and micro-architectural specifications into high-quality RTL implementations.
• Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

• Currently pursuing a Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. Cannot graduate prior to December 2027, and must be available for a 6-month internship.
• Proficiency in System Verilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and develop sign-off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

• Experience with HBM, DRAM, or memory-centric SoC designs.
• Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$38.84 - $50.24 an hour

Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training.

The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

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