Digital Design: SerDes Digital IP Design Engineer

Digital Design:
Ser Des Digital IP Design Engineer

Oversees definition, design, verification co‑definition, and documentation for Ser Des development. Performs architecture design, RTL development, constraints, synthesis, timing analysis, verification, documentation, and support for Ser Des designs. Knowledge of all aspects of the process flow from high‑level RTL design to synthesis, RTL/netlist audits (using tools such as Spyglass), formal verification, constraints development and analysis with emphasis on CDCs in the context of synthesis and overall use in Prime Time, timing model generation (ETM/.db).

Emphasis on Spyglass lint, CDC, and abstract model generation along with design constraint and timing analysis.

Synthesis flows (design compiler or newer tools), lint and CDC analysis (Spyglass), constraints development and timing model creation (Prime Time) along with formality is desired. Knowledge of Ser Des architecture and protocols is a plus. Knowledge of Spyglass, VC Spyglass, design compiler, and Prime Time is a must.

Works on significant and unique development and support issues where analysis of situations or data requires an evaluation of intangibles along with an in‑depth understanding of the underlying designs and implementation techniques used. Exercises independent judgment in methods, techniques and evaluation criteria for obtaining results. Creates formal networks involving coordination among groups and works well with individuals and teams spread across geographical time‑zones.

Acts independently to determine methods and procedures on new or special assignments. May supervise the activities of others. Works in close collaboration with supervisor and can effectively context‑switch and multi‑task based on business needs.

• Bachelors in Electrical/Electronics engineering with at least 12 years or more experience in a relevant field, or Masters in Electrical/Electronics engineering with at least 10 years or more experience in a relevant field.
• Familiarity with VLSI design tools for lint, CDC, synthesis, DFT insertion, timing analysis and scripting languages.
• Proficiency in UNIX/Linux.

The annual base salary range for this position is $127,100 - $203,400. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.

The company follows all applicable laws for Paid Family Leave and other leaves of absence.