Digital Design RTL Engineer

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
• High proficiency in System Verilog
• Proven track record of delivering high-quality System Verilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques.

• BSEE required, MSEE/PHD preferred
• 5+ years of industry experience with a focus on SoC integration, LPDDR5/6, DDR4/5 and/or high-speed Ser Des, or HBM protocols is highly preferred.

The annual base salary range for this position is $91,000 - $146,000.

As a valued member of our team, you will be eligible for a discretionary annual bonus and the opportunity to receive a competitive new hire equity grant, as well as annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package:
Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.