Digital Design: SerDes Digital IP Design Engineer

Digital Design:
Ser Des Digital IP Design Engineer

Oversees definition, design, verification co‑definition, and documentation for Ser Des development.

• Architect and develop RTL, apply constraints, synthesis, and timing analysis.
• Verify designs and provide documentation and support for Ser Des implementations.
• Audit RTL/netlists (e.g., Spyglass), perform formal verification, and drive CDC and model generation using Primetime.
• Develop timing models (ETM/.db) and perform constraint and analysis work emphasizing CDCs in the synthesis context.
• Identify and resolve complex design and support issues requiring in‑depth analysis and coordination across time zones.

Works on significant and unique development and support issues where analysis of situations or data requires evaluation of intangibles along with an in‑depth understanding of underlying designs and implementation techniques. Exercises independent judgment in methods, techniques, and evaluation criteria to obtain results. Creates formal networks involving coordination among groups and works well with individuals and teams spread across geographical time‑zones.

Acts independently to determine methods and procedures on new or special assignments. May supervise the activities of others. Works in close collaboration with a supervisor and can effectively context‑switch and multi‑task based on business needs.

• Bachelors in Electrical/Electronics engineering with at least 12 years of relevant experience, or Masters in Electrical/Electronics engineering with at least 10 years of relevant experience.
• Familiarity with VLSI design tools for lint, CDC, synthesis, DFT insertion, timing analysis, and scripting languages.
• Proficiency on UNIX/Linux platforms.
• Knowledge of synthesis flows (Design Compiler or newer tools), lint and CDC analysis (Spyglass), constraints development and timing model creation (Prime Time), along with formality.
• Knowledge of Ser Des architecture and protocols is a plus.
• Experience with Spyglass, VC Spyglass, Design Compiler, and Prime Time is required.

The annual base salary range for this position is $127,100 – $203,400. The position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package, including medical, dental and vision plans, 401(k) participation with company matching, Employee Stock Purchase Program, Employee Assistance Program, company‑paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.