ASIC DFT Engineer

Job Overview

Broadcom's ASIC Product Division (APD) is seeking a DFT Engineer to lead DFT programs from specification through release at our Fort Collins, Colorado, Development Center. The candidate will work on various phases of SoC DFT related activities – DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post‑silicon debug, and yield improvement to meet product test metrics.

• Understand Broadcom & customer DFT feature requirements & DPPM goals and define appropriate DFT specifications for the ASIC.
• Implement DFT, including scan, MBIST, TAP, LBIST, I/O, Ser Des and other I/P DFT integration.
• Conduct ATPG & verification at the chip level, rapid bring‑up at ATE, and provide RMA support.
• Generate, verify, debug test vectors before tape release and validate testing on ATE during silicon bring‑up.
• Assist with silicon failure analysis, diagnostics & yield improvement efforts.
• Interface with customers, physical design and test engineering/manufacturing teams globally.
• Debug customer‑returned parts on the ATE.
• Innovate newer DFT solutions to solve testability problems in 3nm & beyond.
• Automate DFT & test vector generation flows.

• Strong background in DFT (IO, analog, ATPG, scan, BIST, etc.).
• Experience with scan insertion and scan compression tools (DFT Compiler, Mentor Test Kompress, etc.).
• Proficiency in ATPG vector generation, simulation, and debugging (Tetra Max, Fastscan).
• Verilog coding and testbench generation & simulation experience.
• Memory BIST insertion and verification on embedded memory (SRAM, CAM, eDRAM, ROM).
• Knowledge of IEEE
  1149.1 & IEEE
  1149.6, test‑STA, constraints, IEE
  1687, IJTAG, ICL & PDL.
• Strong skills in analog & digital circuit design, device physics, Si processing, synthesis and transistor reliability.
• Excellent problem‑solving, debug, root‑cause analysis & communication skills.
• Knowledge of statistical process control and data analysis for silicon yield improvements.
• Project management capabilities to track and prioritize competing deliverables across cross‑functional stakeholders.
• Experience working on ATE is a plus.
• Experience with Ser Des, DDR, PCIe, ENET, CXL, IOBIST verification and silicon debug is a plus.
• Experience working on Tessent SSN is a plus.
• Ability to work in a multi‑disciplined, cross‑department environment.

• Bachelor’s in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience, OR Master’s in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience.

• Annual base salary range: $108,000 – $172,800.
• Eligible for a discretionary annual bonus and equity according to plan documents.
• Medical, dental & vision plans; 401(k) with company matching;
  Employee Stock Purchase Program;
  Employee Assistance Program; paid holidays, sick leave, vacation time.
• Paid Family Leave and other eligible leaves in accordance with applicable laws.

Broadcom is proud to be an equal‑opportunity employer. We consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law. We also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside the USA, please be sure to fill out a home address as this will be used for future correspondence.