Digital Design RTL Engineer

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand‑off.
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule.

• High proficiency in System Verilog.
• Proven track record of delivering high-quality System Verilog RTL in advanced process nodes (5nm and below) and deep understanding of PPA optimization, CDC analysis, and low‑power design techniques.
• Bachelor of Science in Electrical Engineering (BSEE) is required;
  Master of Science (MSEE) or PhD is preferred.
• 5+ years of industry experience focusing on SoC integration, LPDDR5/6, DDR4/5, high-speed Ser Des, or HBM protocols is highly preferred.

The annual base salary range for this position is $91,000 - $146,000.

• Discretionary annual bonus.
• Competitive new hire equity grant and annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company match.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.
• Paid family leave and other leaves of absence as required by law.

Broadcom is an equal opportunity employer. Qualified applicants will be considered without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or other federally, state, or locally protected characteristics. Criminal background checks will be considered in compliance with applicable laws.