VLSI Design Verification Manager - Slingshot ASIC Team

Position

VLSI Design Verification Manager – Slingshot ASIC Team

Location:

Onsite; primarily at HPE office.

• Lead a team of 8–15 design verification engineers for Slingshot networking ASICs.
• Define, own, and evolve verification methodology across block, subsystem, and full‑chip scopes.
• Ensure development of robust System Verilog/UVM‑based environments, including stimulus, scoreboards, checkers, assertions, and functional coverage.
• Drive regression health, failure triage, root‑cause isolation, and design issue closure in collaboration with logic design and architecture teams.
• Manage project deliverables, schedules, and staffing to meet program milestones and quality goals.
• Recruit, mentor, and develop engineers; set performance expectations and support career growth.
• Identify and drive opportunities for process improvement, reuse, automation, and verification workflow efficiency.
• Communicate verification status, risks, and readiness clearly to management and cross‑functional partners.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• 10+ years of experience in VLSI design verification, with strong hands‑on background in pre‑silicon DV.

• Strong understanding of System Verilog and UVM‑based verification methodologies.
• Demonstrated technical leadership in design verification – e.g., DV technical lead, block or project verification owner.
• Ability to lead engineers through influence, technical credibility, mentorship, and clear communication.
• Experience with verification planning, coverage‑driven verification, regression management, and sign‑off readiness.
• Proficiency with DV workflows using industry EDA simulation tools.
• Strong analytical and problem‑solving skills.
• Excellent written and verbal communication skills.
• Ability to operate effectively in a multi‑site, cross‑functional engineering environment.

• Previous people‑management experience, including hiring, coaching, and performance management.
• Direct experience with Synopsys VCS large‑scale regression execution, triage workflows, and performance/throughput optimization.
• Familiarity with Git Hub Enterprise Cloud development workflows and AI tools.
• Familiarity with high‑performance networking, Ethernet, SERDES, PCIe, or HPC/AI systems.
• Experience improving verification efficiency through automation, reuse, or methodology refinement.

Health, well‑being, personal & professional development, unconditional inclusion, flexibility to manage work and personal needs.

Annual base salary range varies by location: USD 142,000–270,000 in Colorado; USD 135,000–310,500 in Minnesota & Wisconsin. Variable incentives may also be offered.

Hewlett Packard Enterprise is an Equal Employment Opportunity employer and does not discriminate on the basis of race, gender, or other protected categories. HPE will comply with all applicable laws related to employer use of arrest and conviction records and will consider qualified applicants with criminal histories. No candidate will be charged a registration or hiring fee by HPE or its authorized recruitment agencies.