Defect Engineer

Job Overview

As a Defect Engineer within the Wireless Semiconductor Division (WSD) at Broadcom Inc., you will play a critical role in identifying, analyzing, and minimizing defectivity within our FBAR filter fabrication process. Utilizing inline visual inspection and physical analysis data, you will separate killer from cosmetic defects, map out defect Pareto charts, and provide actionable insights to the cross‑functional fab team. Your work directly minimizes yield loss and reliability failures downstream at wafer sort, assembly, test, and the end customer.

• Establish Technology Baselines:
  Utilize advanced metrology and physical analysis data (SEM, TEM, AFM, FIB) to define baseline defectivity and establish Pareto charts for new and existing technologies.
• Identify Source Failures:
  Pinpoint offending tools, processes, or facility infrastructure driving defect excursions.
• Excursion Containment:
  Initiate corrective actions (PDCA, 8D), place under‑performing tools down, and issue material containment for non‑conforming or out‑of‑control (OOC) material.
• Lab Characterization:
  Partner with the Physical Analysis Lab (PAL) and bench testing teams to submit jobs and successfully characterize unique defect signatures.
• Process Improvement:
  Partner with integration and process engineers to improve defect performance and identify new defects on emerging process nodes.

• Own the Visual Control Plan:
  Define line partitioning, monitoring, and sampling strategies using Klarity and Statistical Process Control (SPC) to maintain stringent fab defect controls.
• Author OCAPs:
  Write and maintain Out‑of‑Control Action Plans (OCAPs) to establish standard operational responses to defect shifts.
• Material Disposition:
  Act as the primary engineering escalation point to disposition OOC material that falls beyond the scope of engineering technicians.
• Identify and characterize novel defect modes through detect, contain, eliminate procedures.

• Lead task forces:
  Facilitate and lead cross‑functional engineering teams investigating complex trend shifts and high‑volume defectivity issues.
• Lead model building activities to hypothesize and validate root causes of defectivity.
• Train and Mentor:
  Train operations staff on material disposition and mentor engineering technicians in advanced defect identification and characterization techniques.
• Quality First Mindset:
  Actively drive a low‑defect, "quality before speed and cost" culture across the entire fab footprint.

• Education:
  
  BS in Electrical Engineering, Materials Science, Physics, Chemistry, or a related engineering field.
• Experience:
  
  8+ years in high‑volume wafer fabrication, specifically within process engineering, defect engineering, or yield enhancement.
• Technical Expertise:
  Strong working knowledge of multiple semiconductor fabrication process modules (e.g., photo, etch, deposition, CMP, test); expertise with Klarity defect analysis software and Statistical Process Control (SPC); advanced proficiency using JMP for statistical data analysis and engineering problem‑solving.
• Leadership & Drive:
  Proven track record of independently facilitating cross‑functional teams to resolve highly complex manufacturing problems.
• Communication:
  Demonstrated ability to communicate technical data clearly and concisely, both verbally and in writing, to audiences ranging from cleanroom operators to fab executives.
• Soft Skills:
  
  Detail‑oriented multitasker with strong self‑awareness—knows when and who to ask for cross‑functional help.

• Education:
  
  MS or PhD in Electrical Engineering, Materials Science, Physics, Chemistry, or a related field.
• Experience:
  
  12+ years in high‑volume semiconductor manufacturing.
• Advanced Material Analytics:
  Direct hands‑on tracking and root‑cause identification using physical analysis lab (PAL) tool outputs (SEM, TEM, AFM, FIB).
• Data Automation & Programming:
  Proficiency in programming languages (e.g., Python, SQL); experience with Python data structures (Pandas/Num Py), spatial math, geometric logic, and parsing raw…