Physical Design Engineer - STA Design Integration

Junior To Mid Level Sta Design Integration Engineer

Insight Global is looking for Junior to Mid level STA Design Integration Engineers for a world class semiconductor ASIC provider. As a STA DI Engineer you will join a highly skilled team of engineers that own the timing analysis and sign-off of complex ASICs. You will be responsible for the day-to-day timing closure and sign-off of complex ASIC designs, run and analyze static timing analysis (using tools like Synopsys Prime Time or Cadence Tempus), debug timing violations such as setup/hold failures, and refine or create timing constraints to accurately model real chip behavior.

You will investigate issues related to clock distribution (including PLLs and clock trees), signal integrity, and RC effects, while interpreting detailed timing reports and tool warnings to identify root causes. The role also involves writing scripts (Python, TCL, Bash) to automate flows, process large datasets, and improve efficiency, as well as leveraging knowledge of circuit elements like flip-flops, latches, memory, and CMOS logic to understand timing paths.

This is a direct hire position sitting out of the Fort Collins, CO location, and offering between $107k - $200k based on experience. The role also offers bull benefits package, annual bonuses, substantial RSU packages, and full relocation provided.