DFT ATPG Design and Test Engineer Job Fort Collins area,Colorado USA,Engineering

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At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whether you’redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward.

Join us and, together, we’ll advance your career.

THE ROLE:

The Cores Organization develops high-performance CPU cores and cache technologies that power AMD's server, client, and gaming products. We are seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation cores and caches.

In this role, you will own scan test pattern delivery, support product test bring‑up, improve scan architecture and coverage, and partner closely with design, physical design, and product test teams to solve complex technical challenges and improve product quality.

THE PERSON:

You are an analytical, detail-oriented engineer who enjoys solving complex technical problems and driving continuous improvement. You take ownership of long‑term deliverables, communicate effectively across teams, and challenge established approaches to improve quality and execution. You are eager to expand your knowledge of CPU and cache technologies and thrive in a collaborative environment that values innovation, learning, and technical growth.

KEY RESPONSIBILITIES:

Own the generation, validation, and delivery of scan test patterns for next‑generation CPU cores and caches.
Partner with product test teams during test bring‑up and troubleshoot pattern, model, and netlist issues.
Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
Collaborate with physical design engineers to support design closure through static timing, clock‑domain crossing, netlist, and power analysis.
Address DFT requirements for high‑frequency CPU designs while minimizing performance impact.
Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
Develop and implement improvements that simplify design complexity and strengthen engineering quality.
Contribute to the continued evolution of CPU cache array and DFT design practices.

PREFERRED EXPERIENCE:

Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.
Strong working knowledge of industry‑standard ATPG tools and their application to pattern generation, fault coverage, and product quality.
Experience debugging ATPG patterns, scan structures, test models, and gate‑level netlists.
Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built‑in self‑test concepts.
Experience with multi‑clock and multi‑power‑domain designs.
Familiarity with static timing analysis, clock‑domain cross‑analysis, static power analysis, and physical design closure.
Experience adapting standard DFT tools or methods to meet performance requirements of high‑frequency designs.
CPU or cache architecture experience is preferred; strong DFT candidates from related ASIC environments may also be considered.
Demonstrated success collaborating across design, physical design, product engineering, and geographically distributed teams.
Interest in continuous improvement and in developing broader expertise across CPU, cache, and silicon design disciplines.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree in Electrical Engineering, Computer…