Senior FPGA Design Engineer

Company Overview

Raytheon Technology is dedicated to defending our nation and allies through advanced engineering solutions. The Multi‑Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics sub‑assemblies for missiles, radars, and electronic warfare systems.

Senior FPGA Design Engineer – MPD Department, Fort Wayne, IN (Onsite). The role requires U.S. citizenship and an active DoD Secret security clearance (existing after day1).

Fort Wayne, Indiana. Relocation assistance is available for eligible candidates.

• Provide full lifecycle support for production quality FPGA designs for all major vendors and device families, including AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro, or Libero.
• Generate FPGA designs for gigabit serial interfaces, RF DSP, controls, data links, embedded processing, and processor interfaces.
• Translate system‑level requirements into FPGA requirements.
• Architect FPGA‑based systems to determine parts, interfaces, and Concept of Operations (CONOPS).
• Lead FPGA designs and write VHDL code for reliability and maintainability.
• Verify designs using self‑checking techniques with directed and constrained random tests, tracking functional and code coverage.
• Define schedules for FPGA tasking and drive execution to the planned budget and schedule.
• Create complete documentation including requirements, verification plan, and user guides.
• Lead individual designs or small teams with minimal oversight.
• Support internal and external technical reviews.
• Engage in knowledge transfer activities and mentor junior engineers.

• Degree in a STEM field and a minimum of 5 years of relevant experience.
• Experience in FPGA/ASIC design (VHDL and/or Verilog) or verification (System Verilog).
• Hands‑on experience with AMD (Xilinx), Altera, and/or Microchip (Microsemi) devices and corresponding tools.
• Experience with timing closure, clock‑domain crossing, reset‑domain crossing, and constraint development.
• Experience with integration and debugging of FPGA/ASIC in a lab environment.
• Experience with source code management, design reviews, and code release in a team development environment.

• Advanced degree in Electrical Engineering or a related STEM major.
• FPGA/ASIC design experience in radar or image processing, embedded systems using ARM, Micro Blaze, or NIOS, gigabit serial interfaces, multi‑gigabit transceivers, constrained random verification in UVM, High‑Level Synthesis (HLS).
• Experience with vector processors and/or GPUs.
• Demonstrated ability to lead teams to achieve schedule, budget, and technical commitments.
• Experience with project management tools such as Earned Value or Agile Execution.
• Proposal development experience.

• Medical, dental, vision, life insurance, short‑term disability, long‑term disability, 401(k) match, flexible spending accounts.
• Flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, holidays.
• Eligibility for annual short‑term and long‑term incentive compensation programs.

USD 86,800 – 165,200 per year (range reflects all experience levels).

Requires U.S. citizenship and an active DoD Secret clearance (existing after day1).

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status. RTX provides affirmative action for qualified individuals with a disability and protected veterans in compliance with Section
503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.