Principal FPGA​/ASIC Verification Engineer; Onsite

Responsibilities

• Verification environment architecture and design using System Verilog with OVM/UVM.
• Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking.
• Testbench development for the verification of RTL blocks using VHDL or System Verilog.
• Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA verification flow.
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status.

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience.
• Active and transferable U.S. government issued security clearance is required prior to start date.
• U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• At least 4+ years experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Demonstrated ability to work independently and lead and/or mentor junior engineers within a team environment.
• Proven ability to design, implement, and execute verification test benches for RTL blocks using VHDL and/or System Verilog.
• 4+ years of experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (System Verilog).
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
• Experience with ASIC/FPGA lab validation and debug using standard lab equipment, familiarity with DFT, manufacturability, and production test concepts (preferred).
• Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as Questa Sim, Synplify, Quartus, or Vivado (preferred).
• Strong written and verbal communication skills, with the ability to work independently and collaboratively in fast-paced, multidisciplinary engineering environments (preferred).

• Medical, dental, and vision insurance.
• Three weeks of vacation for newly hired employees.
• Generous 401(k) plan that includes employer matching funds and separate employer retirement contribution, including a Lifetime Income Strategy option.
• Tuition reimbursement program.
• Student Loan Repayment Program.
• Life insurance and disability coverage.
• Optional coverages: pet insurance, home and auto insurance, additional life and accident insurance, critical illness insurance, group legal,  protection.
• Birth, adoption, parental leave benefits.
• Ovia Health, fertility, and family planning.
• Adoption Assistance, Autism Benefit.
• Employee Assistance Plan, including up to 10 free counseling sessions.
• Healthy You Incentives, wellness rewards program.
• Doctor on Demand, virtual doctor visits.
• Bright Horizons, child and elder care services.
• Teladoc Medical Experts, second opinion program, and more.
• Relocation assistance.

The salary range for this role is $107,500 USD - $204,500 USD. The salary range provided is a good faith estimate representative of all experience levels.

This role is a U.S.

-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.