Principal Silicon Architect

Own the architecture of Oplexa’s processing-element grid from cycle-approximate simulation through FPGA validation and toward ASIC tape-out. You will work directly with the founder on instruction set, dataflow, and compiler co-design decisions, not inherit someone else’s architecture and optimize around the edges.

• Processing-element and dataflow architecture for Edge 1
• FPGA validation before ASIC implementation
• Instruction-set and compiler co-design
• Transformer-native inference architecture
• Architectural trade-offs around performance, efficiency, and implementation

The screening process is a real technical assignment: a cycle-approximate simulator for an 8×8 processing-element grid.

Oplexa is developing Edge 1 as a transformer-native inference architecture for private and edge AI workloads. The architecture is being validated through modeling, simulation, and FPGA work before progressing toward production silicon. This role is focused on architecture ownership and the decisions that shape the silicon itself.