Senior Test Engineer, CMOS Backplane, Raxium

Senior Test Engineer, CMOS Backplane, Raxium

_corporate_fare_ Google _place_ Fremont, CA, USA

** Mid*
* Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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* Minimum qualifications:

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* + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.

+ 4 years of experience with Silicon, CMOS, and IC test development.

+ 3 years of experience with Silicon test hardware, software debugging, and data analysis in a Research and Development (R&D)  or manufacturing environment.

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* Preferred qualifications:

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* + Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).

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Experience with testing software development, Python, and SQL databases, and familiarity with Linux and Ubuntu.

+ Familiarity with test instruments such as power supply, current meter, voltage meter, digital meter, spectrometer, and other electrical lab equipment.

+ Familiarity with firmware concepts, low-level register programming (bare metal programming in C/C++ for microcontrollers), I2C and SPI, and SRAM memory test patterns.

+ Knowledge of electrical engineering fundamentals (CMOS and register-level understanding), power management, display architecture, and video standards (e.g., HDMI or MIPI).

** About the job*
* Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $231000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google () .

** Responsibilities*
* + Develop, validate, optimize standards and engineering CMOS Backplane test solutions for microLED display panels, including CMOS control software solutions. Ensure software test platform and architecture meet the needs of fast moving production and R&D environments.

+ Interface with wafer-level probe cards, test equipment, and instrumentation to facilitate Complementary Metal-Oxide-Semiconductor (CMOS)/Silicon testing and characterization.

+ Identify, diagnose, resolve electrical issues during wafer-level testing using digital oscilloscopes and other testing equipment.

+ Collaborate with CMOS and panel test engineering teams to define and implement high-speed, automated testing solutions for IC/Silicon/CMOS and microLED displays, and debug process plans for manufacturing. Optimize these solutions to ensure test coverage and minimize the test cost.

+ Work with the Test Engineering team to enhance and develop test frameworks based on requirements from the Reliability Team.

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