Senior Wafer Test Hardware Engineer, Raxium

Senior Wafer Test Hardware Engineer, Raxium

Location:

Fremont, CA, USA

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
• 5 years of experience in writing semiconductor functional tests, including register‑level writes/reads and validation on production data.
• 2 years proven experience with wafer‑level probe technologies, including troubleshooting and failure analysis.
• Experience validating hardware and software paths, including step‑by‑step component validation (e.g., verifying pin‑to‑pad contact and communication).

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
• Experience with reliability hardware bring‑up and qualification.
• Experience driving hardware specifications with external equipment vendors.
• Experience with data analysis and visualization tools such as JMP, Python, or SQL.
• Proficiency in structuring semiconductor test data streams, automating data ingestion and designing data visualizations or dashboards for operational monitoring.
• Ability to lead technical projects autonomously and drive alignment across teams (Hardware, Silicon design, Data/IS, and Manufacturing).

• Drive the specification process for a parallel wafer‑level test tool, coordinating with internal teams on pad accommodations and initial bring‑up plans.
• Define and execute the hardware/software validation path, verifying individual vendor components (such as single‑die verification or pin‑to‑pad communication) independently from the complete solution.
• Define input and output data streams with vendors, and coordinate test and information systems (IS) infrastructure to manage and transfer massive die‑level datasets.
• Define the operational flow, integrate the reliability tool with the manufacturing execution system (MES), and establish clear standard operating procedures (SOPs).

US: $159,000 - $231,000 (USD) + 15% bonus target + equity + benefits.

Google’s custom‑designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting‑edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you are sure it meets Google’s standards of quality and reliability.

Google’s Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light‑field display. With start‑up roots and a state‑of‑the‑art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next‑generation display markets.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google’s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement…