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Staff Engineer - AI and Compute Server Design

Job in Fremont, Alameda County, California, 94537, USA
Listing for: SYNNEX Corporation
Full Time position
Listed on 2026-07-24
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 186000 - 245000 USD Yearly USD 186000.00 245000.00 YEAR
Job Description & How to Apply Below

Core Responsibilities

  • Lead board‑and system‑level hardware design.
  • Own schematic design, layout direction, component selection, and board bring‑up for GPU head nodes and compute servers, including power delivery, high‑speed signaling, and management subsystems.
  • Translate requirements into architecture and partner directly with Hyperscalers to convert system‑level and hardware requirements into executable engineering specifications and platform architectures.
  • Drive full product lifecycle execution, lead designs through EVT, DVT, and PVT phases, including signal‑integrity/power‑integrity analysis, design reviews, and risk assessment, ensuring performance, reliability, and manufacturability.
  • Support manufacturing ramp and deployment, collaborate with Operations, MFG, and Quality teams to scale from prototype to high‑volume production, and support datacenter deployment with rapid issue triage and corrective action.
  • Provide technical leadership, mentor engineers, establish best‑practice workflows for schematic reviews, documentation, and validation, and lead complex root‑cause debug across hardware, firmware, and system‑integration domains.
Required Qualifications & Skills
  • Education:

    Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or a related field.
  • Experience:

    10+ years of hardware design experience, including board‑and system‑level engineering, with proven ownership of high‑performance server or GPU/accelerator designs from concept through production.
  • Direct experience with Hyperscalers or large cloud providers strongly preferred.
  • Technical expertise:
    Deep understanding of high‑speed interfaces (PCIe Gen5/6, CXL, NVLink, Ethernet), power delivery networks, SI/PDN design, thermal considerations, and complex multi‑board systems; demonstrated success leading EVT/DVT/PVT validation and manufacturing ramp.
  • Systems thinking:
    Ability to architect and debug complex interactions across CPUs, GPUs, accelerators, system fabrics, firmware, and rack‑level ecosystems.
  • Communication:
    Expert at working across multi‑functional teams, influencing without authority, and representing engineering decisions to technical leaders and executives.
Compensation

$186,000 to $245,000 D.O.E.

EEO Statement

Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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