Senior SI​/PI Engineer - AI and Compute Server Design

Core Responsibilities

• Signal integrity analysis: perform pre- and post-layout SI analysis for high-speed interfaces including PCIe Gen5/Gen6, CXL, NVLink, Ethernet/Ser Des, and DDR5/DDR6 memory, defining channel budgets, routing rules, and equalization strategies.
• Power integrity analysis: design and validate PDN, including PDN impedance targeting, decoupling strategy, and IR‑drop analysis for high-current GPU, CPU, and VR rails.
• Modeling and simulation: build and run models using tools such as HFSS, ADS, HSPICE, Sigrity, and develop IBIS‑AMI and S‑parameter-based channel simulations.
• Lab validation and correlation: execute measurements with high-speed oscilloscopes, VNAs, TDRs, and BER testers; correlate simulation to lab data and drive corrective design changes.
• Cross‑functional design support: partner with board designers, layout, and mechanical teams to embed SI/PI rules into stackups, routing, connector/cable selection, and support EVT/DVT/PVT bring‑up and debug.

• Education:
  
  Bachelor’s or Master’s in Electrical Engineering or a related field.
• Experience:
  
  6+ years of hands‑on SI/PI experience for servers, GPU platforms, or high‑speed digital systems with proven delivery into production.
• Technical expertise: strong knowledge of high‑speed channel design, PDN design and analysis, connector/cable modeling, and PCB stackup/materials; proficiency with SI/PI simulation tools (HFSS, ADS, HSPICE, Sigrity) and high‑speed lab measurement equipment.
• Standards: familiarity with PCIe, CXL, DDR JEDEC, and Ethernet electrical specifications and compliance methodologies.
• Communication: able to translate analysis into clear, actionable design guidance and collaborate effectively across board, layout, and mechanical teams.

$127,000 to $170,000.

Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability, or protected veteran status.