Director of Applications Engineering

Company

Description:

At Lucid Microsystems, we’re redefining data center power for the AI era. Powered by cutting-edge Low Voltage Monolithic GaN technology, we deliver industry-leading high-efficiency and high-power-density solutions designed for next-generation AI servers. Grounded in reliability, scalability, and technical excellence, our engineering-first culture gives leaders the autonomy to innovate, optimize, and drive measurable impact. If you thrive on solving complex operational challenges and building scalable tech that matters, you’ll fit right in.

Location: Fremont, CA (San Francisco Bay Area preferred; Remote acceptable for exceptional candidates)

Position Type: Full-Time

We are seeking a Director of Applications Engineering to define, evaluate, and bring to market next-generation, high-efficiency GaN based power management solutions. In this hands-on technical role, you will lead bench characterization, system-level validation, and technical customer enablement for advanced Smart Power Stages (SPS) and controllers powering high-performance CPUs and GPUs in AI data center architectures.

You will bridge the gap between silicon design, advanced multi-die packaging, product/test engineering, and tier-1 computing clients. The ideal candidate possesses deep expertise in both Silicon (Si) and Gallium Nitride (GaN) power devices, advanced multi-chip packaging, and Smart Power Stage (SPS) topologies.

• Bench Characterization & Diagnostics: Lead hands-on lab characterization, debugging, and performance optimization of Smart Power Stages, driver ICs, and multiphase controllers under real-world AI workload dynamics.
• Silicon & GaN Evaluation: Evaluate and benchmark high-frequency, high-power density Si and GaN-based power stages, optimizing for power density, transient response, efficiency, and thermal dynamics.
• Cross-Functional Collaboration: Partner closely with IC Design, Package Engineering, Systems Engineering, and Product/Test teams to translate system requirements into silicon/module definitions and resolve complex silicon and packaging anomalies.
• Packaging & Thermal Integration: Provide application-level feedback on advanced power packaging technologies, including QFN, LGA, Fan-Out Panel Level Packaging (FO-PLP), and Chip-Embedded / substrate-embedded architectures
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• Customer Technical Advocacy: Deliver reference designs, evaluation boards (EVBs), application notes, and direct engineering support to top-tier hyperscale and server OEM/ODM hardware teams.

• B.S. in Electrical Engineering (M.S. or Ph.D. preferred with a focus on Power Electronics)
• 10+ years of hands-on experience in high-power management IC development and application engineering.
• Proven track record in high-density power solutions for AI servers, GPUs, CPUs, and enterprise computing
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• Deep technical mastery in both Si-based MOSFETs/IC topologies and GaN power devices
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• Strong familiarity with multiphase buck converters, switched-capacitor architectures, and point-of-load (PoL) topologies.
• Expert-level capability in bench testing, high-bandwidth signal integrity measurements, loss breakdown analysis, thermal imaging, and high-frequency noise troubleshooting.
• Deep understanding of power module assembly, parasitic inductance minimization, thermal dissipation paths, and layout constraints for LGA, QFN, FO-PLP, and chip-embedded packages
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• Direct experience at leading power semiconductor organizations (e.g., Infineon, Renesas, Monolithic Power Systems (MPS), Alpha and Omega Semiconductor (AOS), Analog Devices, or similar).

• Direct experience working on power delivery architectures for low-voltage, ultra-high-current processor rails (e.g., sub-1V, 500A+ transient profiles).
• Strong familiarity with board-level layout design (Altium, Cadence Allegro) and power delivery network (PDN) simulation tools (SIMPLIS, SPICE, Ansys Q3D).
• Based in or willing to travel regularly to the San Francisco Bay Area
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