Gen Digital IC Design Intern — SoC & DSP
Job in
Fremont, Alameda County, California, 94537, USA
Listed on 2026-04-20
Listing for:
Neuralink
Apprenticeship/Internship
position Listed on 2026-04-20
Job specializations:
-
IT/Tech
Computer Science, Hardware Engineer -
Engineering
Computer Science, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
A pioneering technology firm in California is seeking a Digital IC Design Engineer Intern to work on innovative chip design for brain-computer interfaces. The role involves collaborating with engineers to enhance hardware performance and energy efficiency. Ideal candidates will have 2+ years in digital design and proficiency in System Verilog, C/C++, and Python. The position offers a competitive hourly rate of $35 and a comprehensive benefits package, including medical and equity options.
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