Senior Principal Mixed Signal Design Engineer

Date Posted:

Country:
United States of America

Location:

US-CA-GOLETA-B01 ~ 6825 Cortona Dr ~ BLDG B01

Position Role Type:
Onsite

U.S. Citizenship: required

Security Clearance:
None/Not Required

Raytheon Vision Systems is seeking a talented Senior Principal Mixed Signal Design Engineer to join our design team.

This position will be onsite in Goleta, CA.

• Collaborate in a fast-paced multidisciplinary team environment to develop cutting-edge image sensor products.
• Participate in mixed-signal ASIC/ROIC development activities with cross-functional teams including chip architecture, specification, design, verification, validation, fabrication, packaging, debugging, test development, failure analysis, and documentation.
• Design, develop, and characterize ROICs for advanced sensing systems.
• Evaluate various aspects of the process flow from design to synthesis, place and route, timing and power use, as well as determine architecture design, logic design, and system simulation and define module interfaces for simulation.
• Design mixed-signal integrated circuits for image sensors, including analog signal chain, digital timing and image processing, and low-power 12–14 bit on-chip ADCs.
• Guide and coordinate teams of highly skilled engineers in complex, multidisciplinary technical environments and communicate complex technical concepts and program status through briefings and technical reviews with senior government and customer stakeholders, including flag officer-level leadership.

• Experience with IC design flows and familiarity with CAD tools such as Cadence and Mentor Graphics (Siemens), analysis & programming tools such as MATLAB, and programming or scripting languages such as Python.
• High-end UNIX based software design tools for circuit simulation, transistor model extraction, noise analysis, linear design, layout and layout automation, and verification.
• Modeling experience with System Verilog/Real Modelling/Verilog-AMS and coding synthesizable RTL.
• Experience leading program development for commercial, defense, and/or space industries to complete designs on schedule and within allocated budget.
• Experience with semiconductor device physics, semiconductor processing, linear IC design, simulation, layout and testing.
• Experience in full-custom CMOS IC design at the transistor level.
• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 10 years of prior relevant experience or an advanced degree in a related field and a minimum of 7 years of prior relevant experience.

• Advanced digital design skills such as experience with Conformal, experience with Digital-on-top mixed-signal design flow including utilization of Innovus for final chip construction, and experience writing behavioral models for digital circuits and analog/mixed signal interfaces and circuits.
• Experience with IP and circuit blocks such as LVDS transmitters/receivers, low-noise and low-power amplifiers, ADC design, PLL/transmitter design and radiation and cryogenic tolerant design techniques.
• Knowledge of high-end UNIX based software design tools for circuit simulation, transistor model extraction, noise analysis, linear design, layout and layout automation, and verification (preferred).
• Familiarity with ROIC architecture, design concepts, operational control and timing.
• Master or PhD in STEM discipline such as Math, Physics, Electrical Engineering, Systems Engineering, Mathematics, or a related discipline with at least 10-year related experience.

• Values:
  Safety, Trust, Respect, Accountability, Collaboration, and Innovation.
• Robust total rewards package with compensation; healthcare, wellness, retirement, work/life benefits; career development and recognition programs. Includes parental leave, flexible work schedules, achievement awards, educational assistance and child/adult backup care.
• Relocation assistance available.

This position requires security clearance. DCSA Consolidated Adjudication Services handles and adjudicates the security clearance process. More information about Security Clearances can be found on the…