Silicon Physical Design Engineer

Staff Silicon Physical Design Engineer

_corporate_fare_ Google _place_ Mountain View, CA, USA;
Goleta, CA, USA

** Advanced*
* Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

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Note:

By applying to this position you will have an opportunity to share your preferred working location from the following:
** Mountain View, CA, USA;
Goleta, CA, USA** .

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* Minimum qualifications:

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* + Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.

+ 5 years of experience in physical implementation of high-performance ASICs.

+ Experience building ASIC implementation flows (RTL-to-GDS2).

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* Preferred qualifications:

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* + Master's degree or PhD in Electrical Engineering, or related disciplines.

+ Experience as tech lead driving physical implementation for complex ASIC project(s).

+ Experience in sign-off convergence including STA, electrical checks, and physical verification.

+ Experience managing ASIC implementation vendors and post-silicon quality.

+ Experience in package design and SI/PI analysis and strategies.

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Experience with pre-silicon and post-silicon DFT.

** About the job*
* In this role, you will be a vital member of the quantum electronics team, providing technical leadership in the area of ASIC implementation as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital designers and RF/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors.

You will own the digital RTL-to-GDS2 process, developing standard ASIC implementation flows and using these flows to transform RTL-level designs into fabrication-ready GDS; this will involve leading external implementation teams through the ASIC digital implementation process. You will be involved in vendor selection, vendor program management, Statement of Work (SOW) documentation, and managing foundry and post-silicon vendor activities related to silicon quality.

You will collaborate with adjacent teams and members of the quantum electronics team to contribute to the long-term ASIC strategy.

The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google () .

** Responsibilities*
* + Own the development and maintenance of an industry-standard ASIC implementation flow and use it to perform RTL-to-GDS2 digital physical implementation, including timing constraint generation, synthesis, floor planning, place and route, clock tree synthesis (CTS), design for test (DFT) (Scan, MBIST, BISR), static timing analysis (STA), signal/power integrity (SI/PI), layout versus schematic and design rule checking (LVS/DRC).

+ Collaborate with internal architecture and design team to evaluate tradeoffs of various design approaches at the power/performance/area (PPA) level.

+ Manage program execution of implementation of quantum control electronics ICs with internal team and external vendors, including  backend execution, packaging, schedules, SOWs and documentation commits, sign-off quality metrics, foundry and post-silicon.

+ Contribute to IP evaluation and negotiation of IP contracts.

+ Contribute to ASIC vendor selection process.

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