Engineering - ASIC & FPGA Design Engineering Security Clearance

Position: Engineering - ASIC & FPGA Design Engineering with Security Clearance
Job Summary:

Senior ASIC & FPGA Design Engineer

Location:

Grand Prairie, TX, 75051, United States [About the Role] Join Lockheed Martin Missiles and Fire Control (MFC) as a Senior ASIC & FPGA Design Engineer, where you will drive the innovation and deployment of advanced aerospace and defense solutions. As a technical leader within our Programmable Logic Design team, you'll work on mission-critical systems that safeguard U.S. and allied warfighters. This is your opportunity to directly shape high-performance hardware and contribute to projects with national impact.

[Responsibilities] - Architect, design, and implement robust FPGA/ASIC solutions that meet stringent performance, safety, and reliability requirements.

- Deliver clean, maintainable RTL code (VHDL, Verilog, System Verilog) and manage comprehensive design documentation.

- Lead synthesis, place and route, and timing closure activities to guarantee optimal device performance.

- Develop and execute rigorous simulation, verification, and validation plans using UVM, SystemC, and Python-based test benches.

- Oversee hardware-in-the-loop testing, board-level debugging, and seamless subsystem integration.

- Conduct timing analysis, power budgeting, and optimize resource utilization for mission-critical applications.

- Maintain configuration control with Git Lab, ensuring full traceability and version management.

- Mentor and guide junior engineers, instilling best practices in design and verification.

- Collaborate cross-functionally with systems, software, hardware, manufacturing, and quality teams to ensure project milestones and integration success. [Required Skills and Experience] - Bachelor's degree in Electrical Engineering or related STEM discipline (Master's preferred) - 3+ years professional experience in FPGA design and simulation verification
- Proficient in VHDL, Verilog, System Verilog
- Skilled in Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and Ultra Scale methodology
- Familiar with FPGA simulation tools such as Synopsys VCS
- Deep understanding of digital design principles: timing analysis, clock domain crossing, signal integrity

- Experience with high-speed interfaces: AXI, Ethernet, TCP/IP, PCIe, serial protocols
- Hands-on laboratory debug experience with oscilloscopes, analyzers, signal generators
- Familiarity with Synopsys EDA tools
- Eligible for DoD Secret clearance [Preferred Skills]

- Experience with LM/MFC and missile defense programs
- Proficient in additional languages and tools: C/C++, MATLAB/Simulink, Synplify, NCSim, Chip Scope
- Knowledge of Micro Semi/Microchip FPGAs and internal IP

- Experience with NSA encryption algorithms (AES, counter mode) - Advanced configuration management in Git Lab - UVM and Simulink/HDL Coder integration
- Strong communication and presentation skills
- Expertise in controls, digital loop-closure, and board-level debugging
- Networking proficiency and use of advanced debugging tools (tcpdump, Wireshark) - Active DoD clearance [Benefits] - Work on high-impact, mission-critical defense projects with next-generation technology
- Collaborate with industry-leading experts in a supportive, inclusive team environment
- Opportunities for career advancement, technical leadership, and mentorship
- Competitive compensation, comprehensive benefits, and security clearance support
- Access to continuous learning, training, and professional development resources [

How to Apply

] Ready to engineer the future of defense? Submit your resume through our Lockheed Martin careers portal. Qualified candidates will be contacted for next steps. Join us and make a difference that matters. JSON